Many digital output or driver circuits have been developed for use in MOS FET(field effect transistor) integrated circuitry, especially for use at output pads (terminals) of microprocessors or microcomputers. A CMOS output buffer having a complementary pair of transistors in an output stage is widely used and operates at a relatively high speed and reduces the internal power consumption when the buffer is in one or the other of its two logic states. However, the basic CMOS output buffer has a disadvantage that an overlapping current passes through the P-channel and N-channel transistor of the output stage in the buffer when it is switching from one logic state to the other.
In addition, it is desirable that the conventional buffer circuit be able to source (and sink) a large amount of current to (and from) external circuitry connected thereto. But, it is difficult to drive external large circuit loads by the conventional CMOS output buffer.
Attempts to overcome such defects of the single transistor pair CMOS output buffer include cross-coupling pre-drivers with input logic gates to provide propagation delays. Others have also connected multiple complementary transistor pairs in parallel in an output stage to increase the source and sink currents. However, such cross-coupling buffer circuits require additional interconnections which undesirably increase the complexity of the circuit, and the propagation delay period of the circuit cannot be controlled. Further, the multiple complementary transistor pair output buffer worsens the overlapping current problem, as described below in detail.